This invention relates to a method of manufacturing a resin-encapsulated semiconductor device and to a resin-encapsulated semiconductor device. In particular, this invention relates to a resin-encapsulated semiconductor device wherein semiconductor elements are mounted facedown on a substrate.
In recent years, the package of resin-encapsulated semiconductor device is increasingly enlarged in scale and the number of the pins (the outer leads) of the package is also increasing. These trends are believed to be further accelerated in future. On the other hand, in order to realize a high density packaging of semiconductor devices so as to miniaturize electronic devices, the semiconductor package itself is requested to be as small and thin as possible.
However, when the number of the pins of the package is increased, the package is inevitably enlarged even if the semiconductor element itself is the same in size, thereby making it difficult to realize a high density packaging of semiconductor devices. Accordingly, a BGA (Ball Grid Array) package which makes it possible to increase the number of the pins without substantially enlarging the size of the package is now increasingly employed. This BGA is constructed such that a bare chip is mounted on an upper surface of a double-sided printed wiring board (substrate) and a two-dimensional array of solder balls is applied to the bottom surface of thereof. The pitch of the terminals in the BGA is made wider than that of QFP (Quad Flat Package) having the same number of pins as that of BGA. As a result, the BGA is advantageous in improving the reliability of a package having a large number of pins.
Additionally, CSP (Chip Size Package) which mounts a bare chip on a double-sided printed wiring substrate like the aforementioned BGA and enables to obtain a micropackage having almost the same size as that of the chip is of great demand particularly in a field where the number of pins is smaller than the BGA. Furthermore, COG (Chip On Glass) wherein a bare chip is mounted on a glass substrate as well as COB (Chip On Board) wherein a bare chip is mounted on a wiring substrate are also widely used since these packaging methods enable the package area to be minimized.
The packages mentioned above are manufactured by mounting a bare chip facedown on a double-sided printed wiring substrate thereby electrically connecting the chip with the circuit via bumps, and then by filling the space between the bare chip and the wiring substrate with a liquid resin. However, since the interval between the bare chip and the wiring substrate is generally very small, i.e. as narrow as several tens micrometers, if the filler contained in the liquid resin is too small in particle diameter, the viscosity of the resin would be increased, thereby making it difficult to fill the space. It is now considered that even when a chip having a dimension of 10 mm.times.10 mm is to be sealed, the liquid resin to be employed for the filling cannot contain more than about 60% of a filler, and that when a chip having a larger dimension than the aforementioned one is to be sealed, the filling by making use of a resin would become more difficult. On the other hand, since a sealing (encapsulating) resin containing a low content of a filler would absorb a lot of water, the encapsulation of semiconductor device with such a sealing resin would invite generation of cracks at the moment of reflow. Further, since the filling of a liquid resin in a space between a semiconductor element and a wiring substrate is effected through a capillary phenomenon based on the surface tension of these materials, the propagation of a sealing resin entering from one of four sides of the chip (semiconductor element) to all of the space may take a long period of time. Moreover, since a sealing resin to be employed in this manner is usually incorporated with an acid anhydride as a curing agent so as to keep it liquid at the normal temperature, it may give rise to the problem of poor reliability of the resultant package.
As for the semiconductor device wherein the space between a semiconductor element and a wiring substrate is filled with a resin of aforementioned composition by means of a so-called potting method, the sides and bottom surface of the semiconductor element are left exposed in contrast to the semiconductor device which is entirely covered with a resin by means of a transfer molding method. Therefore, water may be easily penetrated into an interface between the sealing resin and the wiring substrate or between the sealing resin and the semiconductor element, thus giving rise to various problems including the warpage of the resultant package.
However, the employment of transfer molding method for encapsulating all of a semiconductor element including the sides and bottom surface thereof with a resin is also accompanied with various problems. For example, encapsulation of a flip chip with a resin by making use of a conventional transfer molding method is performed as illustrated in FIG. 1. Referring to FIG. 1, a semiconductor element 35 is mounted via a bump 39 on a wiring substrate 38 having bumps 40, which is then interposed between an upper mold 34 and a lower mold 33, after which a space around the semiconductor element 35 is impregnated with a sealing resin 37. In this case, the resin 37 which has been pressurized in a pot is forced to flow, under a high pressure, through a runner into a cavity, thereby filling spaces between the semiconductor element 35 and the wiring substrate 38, and between the upper mold 34 and the semiconductor element 35. It is generally considered that in order to sufficiently impregnate this narrow space with a resin, a higher pressure than that employed in the ordinary transfer molding method is required. However, there is still a problem that even if a sealing resin is ejected into a cavity under a high pressure, it is difficult to sufficiently transmit the pressure throughout the space since the flow of resin may be restricted at the runner or cavity gate 41, thereby incompletely filling the space with the resin. Furthermore, since a sealing resin is forced to flow from one side gate of cavity, the resin is required to run from one side of the cavity to the opposite side of the cavity, i.e. to run a long distance. As a result, the time required for the molding is prolonged, and under some circumstances, the resin flow is forced to stop halfway. In the case of transfer molding, since a resin is caused to flow from a pot to a cavity via a runner, the mold thereof is rather complicated in structure and large in size, thus making it very difficult to perform the encapsulation of a semiconductor element which is directly mounted on a packaging substrate as in the case of aforementioned COG and COB. Therefore, a mold which is small and simple in structure is required for the manufacture of a micropackage.
Even if the encapsulation of semiconductor device is performed by means of a transfer molding method which enables a semiconductor element to be completely covered by a resin, there is a possibility of producing a product where the sealing resin layer is missing on the bottom surface of the semiconductor element or where the resin covering the semiconductor element is too thin. In such cases, the encapsulated semiconductor element is expected to be easily damaged when a shock is externally applied to the package. It may be possible to avoid such damages by forming a thick resin layer on the bottom surface of the semiconductor element. However, if the resin layer applied to the bottom surface of the semiconductor element is too thick, it will invite various bad influences on the package. For example, due to the cure shrinkage of thick resin layer or due to a difference in thermal expansion coefficient between the thick resin layer and the semiconductor element, the package may be warped. Therefore, the thickness of the sealing resin is required to be delicately controlled for the purposes of enhancing the mechanical strength and preventing the warpage of the package. However, the delicate control in thickness of the sealing resin is difficult due to a problem of poor filling property of the conventional resin composition when it is employed for filling a narrow space. Further, it is difficult to fill a narrow space between a semiconductor element and a packaging substrate with a resin by making use of the conventional transfer molding method.